The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, such scaling down has also been accompanied by increased complexity in design and manufacturing of devices incorporating these ICs. Parallel advances in manufacturing have allowed increasingly complex designs to be fabricated with precision and reliability.
For example, fabrication advances have reduced not only the size of the circuit features but the spacing between the features. However, even when such circuits can be fabricated, other issues may arise due to the reduced space between features. As merely one example, circuit features in close proximity may exhibit electrical effects on one another, such as capacitance and noise, which are exacerbated as the spacing is reduced. Low power devices may demonstrate increased sensitivity to such effects, which in turn, may limit minimum power and maximum performance.